CD4027BD Dual J-K Master-Slave Flip-Flop 20V 200µA IC DIP-16

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CD4027BD Dual J-K Master-Slave Flip-Flop 20V 200µA IC DIP-16 The CD4027BD is a CMOS logic integrated circuit that contains two independent J-K master-slave flip-flops within a single package. Each flip-flop includes J and K data inputs, a clock input, asynchronous set and reset controls, and complementary Q and Q̅ outputs. The master-slave configuration ensures reliable state changes synchronized with the clock signal, preventing unwanted transitions. Thanks to CMOS technology, the CD4027BD offers low power consumption, wide operating voltage range, and excellent noise immunity, making it suitable for both low-power battery devices and industrial digital systems. It is widely used in counters, frequency dividers, memory storage elements, sequencing circuits, and digital control systems, where stable and predictable logic operation is required. Features: Dual independent J-K flip-flops. Master-slave flip-flop architecture. Asynchronous set and reset inputs. Complementary Q and Q̅ outputs. Clock-controlled state switching. Static operation (data retained without clock). CMOS logic technology. High noise immunity. Specifications: Parameter Symbol Value Unit Conditions / Description Logic Type: – Dual J-K Master-Slave Flip-Flop – Functional description Number of Flip-Flops: – 2 – Internal flip-flop count Output Type: – Q and Q̅ – Complementary outputs Trigger Type: – Clock controlled – Master-slave architecture Technology: – CMOS – Logic family Package Type: – DIP-16 – Through-hole package Mounting: – Through-Hole – PCB mounting style Supply Voltage: VDD -0.5 to 20 V Absolute maximum Input Voltage: VIN -0.5 to VDD + 0.5 V All inputs Supply Current: IDD 200 µA VDD = 20V, TA = +125°C Input Current: IIN 1 µA 18V, full temperature Propagation Delay Clock: tPHL / tPLH 130 ns VDD = 10V, CL = 50pF Maximum Clock Frequency: fCL 12 MHz VDD = 15V Operating Temperature: TA -55 to +125 °C Industrial range Pinout: Pin Name Description 1 Q1 Output of Flip-Flop 1 2 Q̅1 Inverted Output of Flip-Flop 1 3 CP1 Clock Input 1 4 R1 Reset 1 5 K1 K Input 1 6 J1 J Input 1 7 S1 Set 1 8 VSS Ground 9 S2 Set 2 10 J2 J Input 2 11 K2 K Input 2 12 R2 Reset 2 13 CP2 Clock Input 2 14 Q̅2 Inverted Output of Flip-Flop 2 15 Q2 Output of Flip-Flop 2 16 VDD Supply Voltage Packages: 1x CD4027BD Dual J-K Master-Slave Flip-Flop 20V 200µA IC DIP-16. Documents: CD4027BD Datasheet