74112 DIP Dual J-K Negative-Edge-Triggered Flip-Flop With Preset and Clear

74112 DIP Dual J-K Negative-Edge- Triggered Flip -Flop With Preset and Clear The 74112 DIP Dual J-K Negative-Edge-Triggered Flip-Flop with Preset and Clear is an integrated circuit designed to provide reliable state changes in digital logic systems. This dual flip-flop configuration allows two independent J-K flip-flops in a single package, making it a compact solution for systems that require multiple flip-flops. The flip-flop is triggered on the negative edge of the clock signal, ensuring precise timing in synchronization applications. It includes both preset and clear inputs, which allow for manual setting or resetting of the flip-flop states, ensuring flexibility in design and function. The J-K flip-flop mechanism enables the toggling of output states based on the J and K inputs, providing more control over the digital circuits. This device is typically used in sequential logic circuits, where reliable state control is needed, such as in counters, shift registers, and memory storage elements. Its versatility, reliability, and integration into standard DIP packages make it an ideal choice for various digital applications. Features: Dual J-K Flip-Flop Configuration. Negative-Edge Triggered Operation. Preset and Clear Inputs for State Control. Compact 16-Pin Package. Suitable for Sequential Logic Applications. Specifications: Parameter Value Package Type: DIP (Dual In-line Package) Number of Pins: 16 Triggering Edge: Negative Edge Logic Type: J-K Flip-Flop Preset and Clear Inputs: Yes Voltage Range: 4.5V to 5.5V Temperature Range: -55°C to 125°C Power Consumption: Low Power 74LS112 Pin Configuration: Pin No Pin Name Description 1 1CLK Clock Input 1 2 1K Input Pin K1 3 1J Input Pin J1 4 1PRE’ Active low Preset Pin 1 5 1Q Output pin Q1 6 1Q’ Active Low output Pin Q1 7 2Q’ Active Low output Pin Q2 8 GND Ground Pin 9 2Q Output pin Q2 10 2PRE’ Active low Preset Pin 2 11 2J Input Pin J2 12 2K Input Pin K2 13 2CLK Clock Input 2 14 2CLR’ Active low clear/Reset pin 2 15 1CLR’ Active low clear/Reset pin 1 16 Vcc Chip Supply Voltage Footprint: Applications: Digital Counters. Memory Storage Elements. Shift Registers. Sequence Generators. Package Contents: 1x 74112 DIP Dual J-K Negative-Edge-Triggered Flip-Flop With Preset and Clear 74112 Datasheet

74112 IC DIP Dual J-K Negative-Edge-Triggered Flip-Flop With Preset and Clear 74LS112 Pin Configuration Pin No Pin Name Description 1 1CLK Clock Input 1 2 1K Input Pin K1 3 1J Input Pin J1 4 1PRE’ Active low Preset Pin 1 5 1Q Output pin Q1 6 1Q’ Active Low output Pin Q1 7 2Q’ Active Low output Pin Q2 8 GND Ground Pin 9 2Q Output pin Q2 10 2PRE’ Active low Preset Pin 2 11 2J Input Pin J2 12 2K Input Pin K2 13 2CLK Clock Input 2 14 2CLR’ Active low clear/Reset pin 2 15 1CLR’ Active low clear/Reset pin 1 16 Vcc Chip Supply Voltage Features: Fully Buffered to Offer Maximum Isolation From External Disturbance Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs Specifications: Number of Circuits: 2 Logic Family: LS Logic Type: J-K Type Flip-Flop Polarity: Inverting/Non-Inverting Input Type: TTL Output Type: TTL High-Level Output Current: -400 uA Low-Level Output Current: 8 mA Supply Voltage Range: 4.5V ~ 5.5V Operating Temperature Range: 0°C ~ 70°C Number of Channels: 2 Number of Input Lines: 5 Number of Output Lines: 2 Reset Type: Set, Reset Mounting Style: Through Hole Package/Case: PDIP-16 74112 Datasheet