PD4164-3 DRAM 65,536 x 1 Bit Memory IC DIP-16

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PD4164-3 DRAM 64K x 1 Bit Memory IC DIP-16 The PD4164-3 is a 65,536-word by 1-bit dynamic N-channel MOS DRAM designed for single +5V operation. It employs a double-poly silicon-gate process and a single-transistor storage cell, maximizing storage density while minimizing power through integrated 512 sense amplifiers and advanced dynamic circuitry. The device internally generates negative substrate bias, making biasing automatic and transparent to the user. Its architecture uses multiplexed address inputs enabling a compact 16-pin DIP package that yields high system bit density and automated handling compatibility. The three-state, non-latched TTL-compatible output is CAS-controlled independently of RAS; holding CAS low preserves output data while RAS performs refresh cycles. A hidden-refresh capability allows CAS to remain low during RAS-only refresh operations. Refresh management covers 128 refresh cycles using A0–A6 within each 2 ms period, and supports normal read/write, read-modify-write, RAS-only refresh and page-mode operation. Designed with low power in mind, it balances refresh timing and circuitry to maximize yield and compatibility across DRAM generations, making it suitable for legacy systems requiring compact, single-bit memory elements. Its design prioritizes manufacturing yield and long-term reliability through conservative refresh characteristics and minimized power dissipation, simplifying integration into memory subsystems and easing maintenance in fielded equipment. Features: High memory density. Multiplexed address inputs. Single +5V supply. On-chip substrate bias generator. Access time options listed (PD4164-1/-2/-3). Read/write cycle time options (PD4164-1/-2/-3). Low power dissipation (active and standby values listed). Non-latched, three-state TTL-compatible output. Read, write, read-write, read-modify-write, RAS-only refresh, and page-mode capability. All inputs TTL compatible and low input capacitance. 128 refresh cycles (A0–A6 pins used for refresh address). CAS-controlled output allowing hidden refresh. Available in ceramic and plastic 16-pin packages. Specifications: Specification PD4164-3 Value Memory Organization: 64K × 1 bit DRAM Memory Cell Type: Single-transistor dynamic MOS Package Type: 16-pin Dual-In-Line Package (DIP) Supply Voltage (VCC): 4.5 V to 5.5 V Typical Supply Voltage: 5.0 V Operating Temperature Range: 0 °C to +70 °C Storage Temperature (Ceramic): –55 °C to +150 °C Storage Temperature (Plastic): –55 °C to +125 °C Access Time (tRAC): 150 ns Random Cycle Time (tRC): 270 ns Page Mode Cycle Time: 170 ns Operating Current (ICC1): 60 mA Standby Current (ICC2): 5 mA Refresh Current (ICC3): 45 mA Page Mode Current (ICC4): 45 mA Active Power Dissipation: 250 mW Standby Power Dissipation: 28 mW Output High Voltage (VOH): ≥ 2.4 V Output Low Voltage (VOL): ≤ 0.4 V Output Short-Circuit Current: 50 mA Addressing Method: Multiplexed row and column Refresh Requirement: 128 cycles within 2 ms Output Type: Three-state TTL compatible Substrate Bias: On-chip generated Pin Configuration: Applications: Main Memory in Early Microcomputers. Video Frame Buffer for Graphics. Memory Expansion Cards. Dedicated Memory for Printers. Industrial Control System Memory. Educational/Training Computer Kits. Package Contents: 1x PD4164-3 DRAM 65,536 x 1 Bit Memory IC DIP-16 Datasheet